View MX98725_5954108.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. features ? a single chip solution integrates 100/10 base-t fast ethernet mac, phy and pmd ? fully comply to ieee 802.3u specification ? operates over 100 meters of stp and category 5 utp cable ? support full and half duplex operation in both 100 base-tx and 10 base-t mode ? fully comply to pci spec. 2.1 with bus clock ranges from 16mhz to 33mhz ? fully comply to advanced configuration and power interface (acpi) rev 1.0 ? fully comply to pci bus power management inter- face spec. rev 1.0 ? magic packet tm mode to support remote-power on and remote-wake-up. ? 100/10 base-t nway auto negotiation function ? large on chip fifos for both transmit and receive operations without external local memory ? bus master architecture with linked host buffers delivers the most optimized performance ? 32-bit bus master dma channel provides ultra low cpu utilization ? proprietary adaptive network throughput control (antc) technology to optimize data integrity and throughput ? support up to 256k bytes boot rom and flash interface ? three levels of loopback diagnostic capability ? support a variety of flexible address filtering modes with 16 cam address and 512 bits hash ? microwire interface to eeprom for customer's ids and configuration data ? single +5.0v power supply, standard cmos tech- nology, 160 pin pqfp package ( magic packet technology is a trademark of advanced micro device corp.) 2. general descriptions the MX98725, second generation of 100/10 base-t single chip mac controller, is designed specifically to meet future demand on fast ethernet networking sys- tem. different from mx98715/715a3, MX98725 addition- ally supports acpi, remote-wake-up, remote-power- on, and up to 256k bytes flash interface to enhance product's added-on value. the mx9725 controller is an ieee802.3u compliant single chip 32-bit full duplex, 10/100mbps highly inte- grated fast ethernet combo solution, designed to ad- dress high performance local area networking (lan) system application requirements. the bus master architecture delivers the performance needed for today high speed and powerful processors technology. in other words, the MX98725 not only keeps cpu utilization low while maximizing data throughput, but it also optimizes the pci bandwidth providing the highest pci bandwidth utilization. to further reduce ownership costs the MX98725 uses drivers that are backward-compatible with the original mxic mx98713 series controllers. the MX98725 contains a pci local bus glueless inter- face, a direct memory access (dma) buffer manage- ment unit, an ieee802.3u-compliant media access con- troller (mac), large transmit and receive fifos, and an on-chip 10 base-t and 100 base-tx transceiver sim- plifying system design and improving high speed signal quality. full-duplex operation are supported in both 10 base-t and 100 base-tx modes that increases the controller's operating bandwidth up to 200mbps. equipped with intelligent ieee802.3u-compliant auto- negotiation, the MX98725-based adapter allows a single rj-45 connector to link with the other ieee802.3u-com- pliant device completely without any need to set con- figuration. in MX98725, an innovative and proprietary design "adaptive network throughput control" (antc) is built- in to configure itself automatically by mxic's driver based on the pci burst throughput of different pcs. with this proprietary design, MX98725 can always optimize its operating bandwidth, network data integrity and through- put for different pcs. 1 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 single chip fast ethernet nic controller preliminary
2 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 mxic MX98725 features remore-wake-up capability and is compliant with the advanced configuration and power interface (acpi). this support enables a wide range of wake-up capabilities, including the ability to cus- tomize which network packets the pc responds to, even when it is in a low-power state. pcs and workstations designed to take advantage of these capabilities can be turned on remotely and serviced simultaneiously over the network from one central server, helping organiza- tions reduce their total cost of ownership of high-perfor- mance business pcs. with its on-chip support for both little and big endian byte alignment, this controller can also address non-pc applications. for diskless applications of networking, remotely boot- ing up is a necessary process. to update or modify the code is such a complex process that network venders or owners must provide a new eprom, replace the ex- isting eprom on the network adaptor and then reboot the computer. thanks to the development of flash memory, MX98725 successfully incorporated flash in- terface to provide remotely boot code update service and that means network maintenance becomes effort- less. 3. pin configurations 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 foeb bpa9 bpa10 bpa11 bpa12 vdd vdd gnd gnd bpa13 bpa14 bpa15 led0 led1 led2 led3 avdd agnd arda avdd ckref agnd agnd avdd agnd agnd avdd avdd rxin rxip avdd avdd agnd agnd avdd txon txop agnd agnd cpk 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 cbeb0 ad8 ad9 gnd gnd ad10 ad11 ad12 vdd vdd ad13 ad14 gnd gnd ad15 cbeb1 pa r serrb perrb vdd stopb devselb trdyb irdyb gnd gnd frameb cbeb2 ad16 ad17 gnd ad18 ad19 vdd vdd ad20 ad21 gnd ad22 ad23 rtx2eq rtx advv agnd agnd avdd agnd avdd agnd reserved laneake exstartb en_pro pmeb intab rstb pciclk gntb reqb ad31 ad30 gnd ad29 ad28 vdd vdd ad27 vdd vdd gnd gnd ad26 ad25 gnd gnd ad24 cbeb3 idsel gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 fcsb fweb bpa8 bpa7 bpa6 bpa5 bpa4 bpa3 bpa2 bpa1(eedi) bpa0(eeck) eecs bpa16 bpa17 bpd0(eed) bpd1 bpd2 bpd3 bpd4 bpd5 bpd6 bpd7 gnd gnd vdd vdd ad0 ad1 gnd ad2 ad3 vdd vdd ad4 ad5 gnd gnd ad6 ad7 gnd MX98725
3 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 4. pin description ( 160 pin pqfp ) ( t/s : tri-state, s/t/s : sustended tri-state, i : input, o : output, o/d : open drain ) pin name type pin no. 160 pin function and driver ad[31:0] t/s 20,21,23,24, pci address/data bus: shared pci address/data bus lines. little or 27,32,33,36, big endian byte ordering are supported. 41,37,38,42, 44,45,48,49, 51,52,66,69, 70,73,74,75, 78,79,82,83, 86,87,90,91, 93,94 cbeb[3:0] t/s 37,53 pci command and byte enable bus: shared pci bus command and 65,80 byte enable bus, during the address phase of the transaction, these four bits provide the bus command. during the data phase, these four bits provide the byte enable. frameb s/t/s 54 pci frameb signal: shared pci cycle start signal, asserted to indicate the beginning of a bus transaction. as long as frameb is asserted, data transfers continue. trdyb s/t/s 58 pci target ready: issued by the target agent, a data phase is completed on the rising edge of pciclk when both irdyb and trdyb are asserted. irdyb s/t/s 57 pci master ready: indicates the bus master's ability to complete the current data phase of the transaction. a data phase is completed on any rising edge of pciclk when both irdyb and trdyb are asserted. devselb s/t/s 59 pci slave device select: asserted by the target of the current bus access. when MX98725 is the initiator of current bus access, the target must assert devselb within 5 bus cycles, otherwise cycle is aborted. idsel i 38 pci initialization device select: target specific device select signal for configuration cycles issued by host. pciclk i 17 pci bus clock input: pci bus clock range from 16mhz to 33mhz. rstb i 16 pci bus reset: host system hardware reset. intab o/d 15 pci bus interrupt request signal: wired to intab line. serrb o/d 63 pci bus system error signal: if an address parity error is detected and cfcs bit 8 is enab led, serrb and cfcss bit 30 will be asserted. perrb s/t/s 62 pci bus data error signal: as a bus master, when a data parity error is detected and cfcs bit 8 is enabled, cfcs bit 24 and csr5 bit 13 will be asserted. as a bus target, a data parity error will cause perrb to be asserted.
4 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 pin name type pin no. 160 pin function and driver par t/s 64 pci bus parity bit: shared pci bus even parity bit for 32 bits ad bus and cbe bus. stopb s/t/s 60 pci target requested transfer stop signal: as bus master, assertion of stopb cause MX98725 either to retry, disconnect, or abort. reqb t/s 19 pci bus request signal: to initiate a bus master cycle request gntb i 18 pci bus grant acknowledge signal: host asserts to inform MX98725 that access to the bus is granted pmeb o/d 14 power management event: asserts low when magic packet is received. exstartb o/d 12 start externel circuit signal: asserts low to enable system's power supply when magic packet is detected. normally tri-stated. lanwake o 11 lan wake up signal: asserts high to indicate a magic packet has been detected in magic packet enable mode. en_rpo i 13 enable on-chip power-on-reset : normally unconnected. bpa1 o 111 boot prom address bit 1(eecs=0): together with bpa[17:0] to access (eedi) external boot prom up to 256kb. eeprom data in(eecs=1): eeprom serial data input pin. bpa0 o 110 boot prom address bit 0(eecs=0): together with bpa[17:0] to access (eeck) external boot prom or flash up to 256kb. eeprom clock(eecs=1): eeprom clock input pin bpa[17:0] o 107,108 boot prom address lines: 110-118 123-125 130-132 bpd0 t/s 106 boot prom data line 0(eecs=0): boot rom or flash data line 0. (eedo) (eeprom data out(eecs=1): eeprom serial data out pin(during reset initialization.) bpd[7:0] t/s 99-106 boot prom data lines: boot rom or flash data lines 7-0. eecs o 109 eeprom chip select. fweb o 119 flash write enable foeb o 121 flash rom output enable fcsb o 120 flash chip select pin rda o 139 connecting an external resistor to ground. see application note. rtx o 2 connecting an external resistor to ground. see application note. rtx2eq o 1 connecting an external resistor to ground. see application note. cpk i 160 connecting an external capacitor. see application note. rxip i 150 twisted pair receive differential input: support both 10base-t and 100 base-tx differential receive input. rxin i 149 twisted pair receive differential input: support both 10base-t and 100 base-tx receive differential input
5 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 pin name type pin no. 160 pin function and driver txop o 157 twisted pair transmit differential output: support both 10 base-t and 100 base-tx transmit differential output txon o 156 twisted pair transmit differential output: support both 10 base-t and 100 base-tx transmit differential output ckref i 141 reference clock: 25mhz oscillator clock input led0 o 133 programmable led pin 0: csr9.28=1 set the led as link speed (10/100) led. csr9.28=0 set the led as activity led. default is activity led after reset. led1 o 134 programmable led pin 1: csr9.29=1 set the led as link/activity led. csr9.29=0 set the led as good link led. default is rx led after reset. led2 o 135 programmable led pin 2: csr9.30=1 set the led as collision led. csr9.30=0 set the led as tx led. default is tx led after reset. led3 o 136 programmable led pin 3: csr9.31=1 set the led as full/half duplex led. csr9.31=0 set the led as rx led. default is rx led after reset. reserved i 10 reserved pin. vdd i 25,26,28,29, digital power pins. 30,46,47,61, 71,72,88,89, 95,96,126,127 gnd i 22,30,31,34, digital ground pins. 35,39,40,43, 50,55,56,67, 68,76,77,81, 84,85,92,97, 98,128,129 avdd i 3,6,8,137, analog power pins. 140,144,147, 148,151,152, 155 agnd i 4,5,7,9,138, analog ground pins. 142,143,145, 146,153,154, 158,159
6 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5. programming interface 5.1 pci configuration registers : 5.1.1 pci id register ( pfid ) ( offset 03h-00h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 device id (bit 31:16) vendor id (bit 15:0) this register can be loaded from external serial eeprom or use a mxic preset value of "0d9" and "0531" for vendor id and device id respectively. word location 3eh and 3dh in serial eeprom are used to configure customer's vendor id and device id respectively. if location 3eh contains"ffff" value then mxic's vendor id and device id will be set in this register, otherwise both 3eh and 3dh will be loaded into this register from serial eeprom. 5.1.2 pci command and status register ( pfcs ) ( offset 07h-04h ) the bit content will be reset to 0 when a 1 is written to the corresponding bit location. bit 0 : io space access, set to 1 enable io access bit 1 : memory space access, set to 1 to enable memory access bit 2 : master operation, set to 1 to support bus master mode bit 5-3 : not used bit 6 : parity error response, set to 1 to enable assertion of csr<13> bit if parity error detected. bit 7 : not used bit 8 : system error enable, set to 1 to enable serr# when parity error is detected on address lines and cbe[3:0]. bit 20 : new capability. set to support pci power management. bit 22-bit19 : not used bit 23 : fast back-to back, always set to accept fast back-to-back transactions that are not sent to the same bus device. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 detect party error signal system error data parity report new capability receive master abort receive target abort deceive select timing fast back-to-back system error enable parity error response master operation memory space access io space access
7 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.1.3 pci revision register ( pfrv ) ( offset 0bh-08h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base class step number subclass revision number bit 3 - 0 : step number, range from 0 to fh. bit 7 - 4 : revision number, fixed to 3h for MX98725 bit 15 - 8 : not used bit 23 - 16 : subclass, fixed to 0h. bit 31 - 24 : base class, fixed to 2h. 5.1.4 pci base io address register ( pbio ) ( offset 13h-10h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 configuration base io address io/memory space indicator bit 0 : io/memory space indicator, fixed to 1 in this field will map into the io space. this is a read only field. bit 7 - 1 : not used, all 0 when read bit 31 - 8 : defines the address assignment mapping of MX98725 csr registers. bit 24:data parity report, is set to 1 only if perr# active and pfcs<6> is also set. bit 26-25:device select timing of devselb pin. bit 27:not used bit 28:receive target abort, is set to indicate a transaction is terminated by a target abort. bit 29:receive master abort, is set to indicate a master transaction with master abort. bit 30:signal system error, is set to indicate assertion of serr#. bit 31:detected parity error, is set whenever a parity error detected regardless of pfcs<6>.
8 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.1.5 pci base memory address register ( pbma ) ( offset 17h-14h ) 5.1.6 pci subsystem id register ( psid ) ( offset 2ch-2fh ) 5.1.7 pci base expansion rom address register ( pber ) ( offset 33h-30h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 configuration base memory address memory spec indicator bit 0 : memory space indicator, fixed to 0 in this field will map into the memory space. this is a read only field. bit 6 - 1 : not used, all 0 when read bit 31 - 7 : defines the address assignment mapping of MX98725 csr registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 subsystem id (31:16) subsystem vendor id (bit 15:0) this register is used to uniquely identify the add-on board or subsystem where the nic controller resides. values in this register are loaded directly from external serial eeprom after system reset automatically. word location 36h of eeprom is subsystem vendor id and location 35h is sub-system id. bit 0 : address decode enable, decoding will be enabled if only both enable bit in pfcs<1> and this expansion rom register are 1. bit 10 - 1 : not use bit 31 - 11 : defines the upper 21 bits of expansion rom base address. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 expansion rom base address (upper 21 bit) address decode enable 0 0 0 0 0 0 0
9 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.1.8 pci capability pointer register ( pfcp ) ( offset 37h-34h ) 5.1.9 interrupt register ( pfit ) ( offset 3fh-3ch ) 5.1.10 pci driver area register ( pfda ) ( 43h-40h ) bit 7- 0 : capability pointer (cap_ptr) is set to 44h if pmeb is connected to pci bus, otherwise 00. bit 31- 8 : reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 capability pointer (set to 44h) bit 7 - 0 : interrupt line, system bios will writes the routing information into this field, driver can use this information to determine priority and interrupt vector. bit 15 - 8 : interrupt pin, fixed to 01h which use inta#. bit 31 - 24 : max_lat which is a maximum period for a access to pci bus. bit 23 - 16 : min_gnt which is the maximum period that MX98725 needs to finish a brust pci cycle. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 min-gnt interrupt pin max_lat 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 interrupt line bit 31 : sleep mode, set to sleep mode which allows access to pci configuration space, a hardwarreset or reset to this bit can exit from sleep mode. magic packet can be received under sleep mode if csr16<21> ( magic packet enable ) is set. bit 30 : not used bit 29 : board type bit 15 - 8 : driver is free to read and write this field for any purpose. bit 7 - 0 : not used. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sleep mode board type driver special use
10 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.1.11 pci power management capability register ( ppmc ) ( 47h-44h ) bit 31- 27 : pme_support, read only indicates the power states in which the function may assert pmeb pin. bit 31 ---- pme_d3cold (value=1) bit 30 ---- pme_d3warm bit 29 ---- pme_d2 bit 28 ---- pme_d1 bit 27 ---- pme_d0 bit 26 : d2 mode support, read only. bit 25 : d1 mode support, read only. bit 24-22 : aux_i bits, auxiliary power reporting, read only. bit 21 : dsi, read only. bit 20 : auxiliary power source, read only. bit 19 : pme clock, read only. bit 18-16 : version, read only. bit 15-8 : next pointer, read only. bit 7-0 : capability id, read only, a 1 indicates that the data structure currently being pointed to is the pci power managment data structure. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 d2_support d1_support pme_support 0 0 0 0 0 0 0 0 aux_i dsi auxiliary power source pme clock version next pointer capability id 5.1.13 pci power management command and status register ( ppmcsr ) ( 4bh-48h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bridge extension support pme_status data data_scale data_select pme_en reserved power state 0 0 0 0 0 0
11 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.2 host interface registers MX98725 csrs are located in the host i/o or memory address space. the csrs are double word aligned and 32 bits long. definitions and address for all csrs are as follows : csr mapping register meaning offset from csr base address ( pbio and pbma ) csr0 bus mode 00h csr1 transmit poll demand 08h csr2 receive poll demand 10h csr3 receive list demand 18h csr4 transmit list base address 20h csr5 interrupt status 28h csr6 operation mode 30h csr7 interrupt enable 38h csr8 missed frame counter 40h csr9 serial rom and mii management 48h csr10 reserved 50h csr11 general purpose timer 58h csr12 10 base-t status port 60h csr13 sia reset register 68h csr14 10 base-t control port 70h csr15 watchdog timer 78h csr16 magic packet register 80h csr20 nway status register a0h bit 1-0 : power_state, read/write. bit7-2 : all 0. reserved. bit8 : pme_en, set 1 to enable pmeb. set 0 to disable pmeb assertion. bit 12-9 : data_select for report in the data register located at bit 31:24. bit 14-13 : data_scale, read only. bit 15 : pme_status independent of the state of pme_en. when set, indicates a assertion of pmeb pin. (support d3 cold). write 1 to clear the pmeb signal. write 0, no effect. bit 21-16 : reserved. bit 22 : b2_b3#, b2_b3 support for d3 hot, meaningful only if bpcc_en = 1, read only. bit 23 : bpcc_en, bus power/clock control enable, read only. bit 31-24 : data, read only.
12 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.2.1 bus mode register ( csr0 ) field name description 0 swr software reset, when set, MX98725 resets all internal hardware with the exception of the configuration area and port selection. 1 bar internal bus arbitration scheme between receive and transmit processes. the receive channel usually has higher priority over transmit channel when receive fifo is partially full to a threshold. this threshold can be selected by programming this bit. set for lower threshold, reset for normal threshold. 6:2 dsl descriptor skip length, specifies the number of longwords to skip between two descriptors. 7 ble big/little endian, set for big endian byte ordering mode, reset for little endian byte ordering mode, this option only applies to data buffers 13:8 pbl programmable burst length, specifies the maximum number of longwords to be trans ferred in one dma transaction. default is 0 which means unlimited burst length, possible values can be 1,2,4,8,16,32 and unlimited . 15:14 cal cache alignment, programmable address boundaries of data burst stop, MX98725 can handle non-cache- aligned fragement as well as cache-aligned fragment efficiently.18:17 tap transmit auto-polling time interval, defines the time interval for MX98725 to performs transmit poll command automatically at transmit suspended state. 21 rme pci memory read multiple command enable, indicates bus master may intend to fetch more than one cache lines disconnecting. 23 rle pci memory read line command enable, indicating bus master intends to fetch a complete cache line. 24 wie pci memory write and invalidate command enable, guarantees a minimum transfer of one complete cache line. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wie-write and invalidate enable ple-read line enable swr-software read ble-big/little endian rme-read multiple enable tap- transmit automatice polling zero-must be zero pbl-programmable burst length 0 dsl-descriptor skip length bar-bus arbitration cal-cache alignment
13 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 table 5.2.0 transmit auto polling bits csr<18:17> time interval 00 no transmit auto-polling, a write to csr1 is required to poll 01 auto-poll every 200 us 10 auto-poll every 800 us 11 auto-poll every 1.6 ms 5.2.2 transmit poll command ( csr1 ) 5.2.3 receive poll command ( csr2 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 transmit poll command field name description 31:0 tpc write only, when written with any value, MX98725 read transmit descriptor list in host memory pointed by csr4 and processes the list. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 receive poll command field name description 31:0 rpc write only, when written with any value, MX98725 read receive descriptor list in host memory pointed by csr4 and processes the list. 5.2.4 descriptor list address ( csr3, csr4 ) csr3 receive list base address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 start of receive list address csr4 transmit list base address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 start of transmit list address
14 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.2.5 status register ( csr5 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rs-receive process state nis-normal interrupt summary lf-link fail eti-early transmit interrupt ais-abnormal interrupt summary eri-early receive interrupt fbe-fatal bus error gte-general purpose timer expired mpi-magic packet interrupt lc-link change rps-receive process stopped ri-receive interrupt eb-error bits ts-transmit process state rwt-receive watchdog timeout ru-receive buffer unavailable lpaci-link pass/autonegotiation completed interrupt unf-transmit underflow tjt-transmit jabber timeout tu-transmit buffer unavailable tps-transmit process stopped ti-transmit interrupt field name description 28 mpi magic packet received interrupt. valid only if csr16<22> bit is set. 27 lc 100 base-tx link status has changed either from pass to fail or fail to pass. read csr12<1> for 100 base-tx link status. 25:23 eb error bits, read only, indicating the type of error that casued fatal bus error. 22:20 ts transmit process state, read only bits indicating the state of transmit process. 19:17 rs receive process state, read only bits indicating the state of receive process. 16 nis normal interrupt summary, is the logical or of csr5<0>, csr5<2> and csr5<6> and csr5<28>. 15 ais abnormal interrupt summary, is the logical or of csr5<1>, csr5<3>, csr5<5>, csr5<7>, csr5<8>, csr5<9>, car5,10>, csr5<11> and csr5<13>, csr5<27>. 14 eri early receive interrupt, indicating the first buffer has been filled in ring mode, or 64 bytes has been received in chain mode. 13 fbe fatal bus error, indicating a system error occured, MX98725 will disable all bus access. 12 lf link fail, indicates a link fail state in 10 base-t port. this bit is valid only when csr6<18>=0, csr14<8>=1, and csr13<3>=0. 11 gte general purpose timer expired, indicating csr11 counter has expired.
15 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 field name description 10 eti early transmit interrupt, indicating the packet to be transmitted was fully transferred to internal tx fifo. csr5<0> will automatically clears this bit. 9 rwt receive watchdog timeout, reflects the network line status where receive watchdog timer has expired while the other node is still active on the network. 8 rps write only, when written with any value, MX98725 reads receive descriptor list in host memory pointed by csr4 and processes the list. 7 ru receive buffer unavailable, the receive process is suspended due to the next descriptor in the receive list is owned by host. if no receive poll command is issued, the reception process resumes when the next recognized incoming frame is received. 6 ri receive interrupt, indicating the completion of a frame reception. 5 unf transmit underflow, indicating transmit fifo has run empty before the completion of a packet transmission. 4 lpanci when autonegotiation is not enabled ( csr14<7>=0 ), this bit indicates that the 10base- t link integrity test has completed successfully, after the link was down. this bit is also set as as a result of writing 0 to csr14<12> ( link test enable ). when autonegotiation is enabled ( csr14<7> =1 ) , this bit indicates that the autonegotiation has completed ( csr12<14:12>=5 ). csr12 should then be read for a link status report. this bit is only valid when csr6<18>=0, i.e. 10 base-t port is selected link fail interrupt ( csr5<12> ) will automatically clears this bit. 3 tjt transmit jabber timeout, indicating the MX98725 has been excessively active. the transmit process is aborted and placed in the stopped state. tdes0<1> is also set. 2 tu transmit buffer unavailable, transmit process is suspended due to the next descriptor in the transmit list is owned by host. 1 tps transmit process stopped. 0 ti transmit interrupt. indicating a frame transmission was completed.
16 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 table 5.2.1 fatal bus error bits csr5<25:23> process state 000 parity error for either serr# or perr#, cleared by software reset. 001 master abort 010 target abort 011 reserved 1xx reserved table 5.2.3 receive process state csr5<19:17> process state 000 stopped- reset or stop receive command fetching receive descriptor 010 checking for end of receive packet 011 waiting for receive packet 100 suspended, receive buffer unavailable 101 closing receive descriptor 110 purging the current frame from the receive fifo due to unavailable receive buffer 111 queuing the receive frame from the receive fifo into host receive buffer table 5.2.2 tranasmit process state csr5<22:20> process state 000 stopped- reset or transmit jabber expired. 001 fetching transmit descriptor 010 waiting for end of transmission 011 filling transmit fifo 100 reserved 101 setup packet 110 suspended, either fifo underflow or unavailable transmit descriptor 111 closing transmit descriptor
17 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.2.6 operation mode register ( csr6 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 coe-collision offset enable fc-force collision mode lom-loopback operation mode tr-threshold control bits st-start/stop transmission command ttm-transmit threshold mode sf-store and forward pr-promiscuous mode hbd-hearbeat disable ps-port select fd-full duplex mode pm-pass all multicast sb-start/stop backoff counter if-inverse filtering pb-pass bad frame ho-hash-only filtering mode sr-start/stop receive hp-hash/perfect receive filtering mode pcs-pcs function scr-scrambler mode field name description 24 scr scrambler mode, default is set to enable scrambler function. not affected by software reset. 23 pcs default is set to enable pcs functions. csr6<18> must be set in order to operate in symbol mode. 22 ttm transmit threshold mode, set for 10 base-t and reset for 100 base-tx. 21 sf store and forward, when set, transmission starts only if a full packet is in transmit fifo. the threshold values defined in csr6<15:14> are ignored 19 hbd heartbeat disable, set to disable sqe function in 10 base-t mode. 18 ps port select, deafult is o which is 10 base-t mode, set for 100 base-tx mode. a software reset does not affect this bit. 17 coe collision offset enable, set to enable a modified backoff algorithm during low collision situation, reset for normal backoff algorithm. 15:14 tr threshold control bits, these bits controls the selected threshold level for MX98725's transmit fifo, transmission starts when frame size within the transmit fifo is larger than the selected threshold. full frames with a length less than the threshold are also transmitted. 13 st start/stop transmission command, set to place transmission process in running state and will try to transmit current descriptor in transmit list. when reset, transmit process is placed in stop state.
18 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 field name description 12 fc force collision mode, used in collision logic test in internal loopback mode, set to force collision during next transmission attempt. this can result in excessive collision reported in tdes0<8> if 16 or more collision. 11:10 lom loopback operation mode, see table. 9 fd full-duplex mode, set for simultaneous transmit and receive operation, heartbeat check is disabled, tdes0<7> should be ignored, and internal loopback is not allowed. this bit controls the value of bit 6 of link code word . 7 pm pass all multicast, set to accept all incoming frames with a multicast des tination address are received. incoming frames with physical address are filtered according to the csr6<0> bit. 6 pr promiscuous mode, any incoming valid frames are accepted, default is reset and not affected by software reset. 5 sb start/stop backoff counter, when reset, the backoff timer is not affected by the network carrier activity. otherwise, timer will start counting when carrier drops. 4 if inverse filtering, read only bit, set to operate in inverse filtering mode, only valid during perfect filtering mode. 3 pb pass bad frames, set to pass bad frame mode, all incoming frames passed the address filtering are accepted including runt frames, collided fragments, truncated frames caused by fifo overflow. 2 ho hash-only filtering mode , read only bit, set to operate in imperfect filtering mode for both physical and multicast addresses. 1 sr start/stop receive, set to place receive process in running state where descriptor acquisition is attempted from current position in the receive list. reset to place the receive process in stop state. 0 hp hash/perfect receive filtering mode, read only bit, set to use hash table to filter multicast incoming frames. if csr6<2> is also set, then the physical adresses are imperfect address filtered too. if csr6<2> is reset, then physical addresses are perfect address filtered, according to a single physical address as specified in setup frame.
19 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 table 5.2.4 transmit threshold csr6<21> csr6<15:14> csr6<22>=0 csr6<22>=1 (threshold bytes) (for 100 base-tx) (for 10 base-t) 0 00 128 72 0 01 256 96 0 10 512 128 0 11 1024 160 1 xx ( store and forward ) table 5.2.5 data port selection csr14<7> csr6<18> csr6<22> csr6<23> csr6<24> port 1 0 x x x nway auto-negociation 0 0 1 x x 10 base-t 0 1 0 1 1 100 base-tx table 5.2.6 loopback operation mode csr6<11:10> operation mode 00 normal 01 internal loopback at fifo port 11 internal loopback at the phy level 10 external loopback at the pmd level table 5.2.7 filtering mode csr6<7> csr6<6> csr6<4> csr6<2> csr6<0> filtering mode 0 0 0 0 0 16 perfect filtering 0 0 0 0 1 512-bit hash + 1 perfect filtering 0 0 0 1 1 512-bit hash for multicast and phyical addresses 0 0 1 0 0 inverse filtering x 1 0 x x promiscuous 1 0 0 x x pass all multicast
20 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.2.7 interrupt mask register ( csr7 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nie-normal interrupt summary enable fbe-fatal bus error enable lfe-link fail enable aie-abnormal interrupt summary enable erie-early receive interrupt enable etie-early transmit interrupt enable rie-receive interrupt enable rwe-receive watchdog enable rse-receive stopped enable gpte-general-purpose timer enable rue-receive buffer unavailable enable une-underflow interrupt enable lpancie-link pass /nway complete interrupt enable tje-transmit jabber timeout enable tue-transmit buffer unavailable enable tse-transmit stopped enable tie-transmit interrupt enable lce-link changed enable mpie-magic packet interrupt enable field name description 28 mpie magic packet interrupt enable, enables csr5<28>. 27 lce link changed enable, enables csr5<27>. 16 nie normal interrupt summary enable, set to enable csr5<0>, csr5<2>, csr5<6>. 15 aie abnormal interrupt summary enable, set to enbale csr5<1>, csr5<3>, csr5<5>, csr5<7>, csr5<8>, csr5<9>, csr5<11> and csr5<13>. 14 erie early receive interrupt enable 13 fbe fatal bus error enable, set together with with csr7<15> enables csr5<13>. 12 lfe link fail interrupt enable, enables csr5<12> 11 gpte general_-purpose timer enable, set together with csr7<15> enables csr5<11>. 10 etie early transmit interrupt enable, enables csr5<10> 9 rwe receive watchdog timeout enable, set together with csr7<15> enables csr5<9>. 8 rse receive stopped enable, set together with csr7<15> enables csr5<8>. 7 rue receive buffer unavailable enable, set together with csr7<15> enables csr5<7>. 6 rie receive interrupt enable, set together with csr7<16> enables csr5<6>. 5 une underflow interrupt enable, set together with csr7<15> enables csr5<5>. 4 lpancie link pass/autonegotiation completed interrupt enable 3 tje transmit jabber timeout enable, set together with csr7<15> enables csr5<3>. 2 tue transmit buffer unavailable enable, set together with csr7<16> enables csr5<2>. 1 tse transmit stop enable, set together with csr7<15> enables csr5<1>. 0 tie transmit interrupt enable, set together with csr7<16> enables csr5<0>.
21 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.2.8 missed frame counter ( csr8 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 missed frame overflow missed frame counter field name description 16 mfo missed frame overflow, set when missed frame counter overflows, reset when csr8 is read. 15:0 mfc missed frame counter, indicates the number of frames discarded because no host receive descriptors were available. 5.2.9 non-volatile memory control register ( csr9 ) field name description 31 led3sel 0:default value. set led3 as rx led. 1: set led3 as full/half duplex led. 30 led2sel 0:default value. set led2 as link speed (10/100) led. 1: set led2 as collision led. 29 led1sel 0:default value. set led1 as good link led. 1: set led1 as link/activity led. 28 led0sel 0:default value. set led0 as activity led. 1: set led0 as link speed (10/100) led. 14 rd boot rom/eeprom read operation select bit. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 led2sel led3sel br-boot rom select data-boot rom data or serial rom control led1sel led0sel rd-read operation sr-serial rom select wr-write operation
22 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 field name description 13 wr boot rom/eeprom write operation select bit. operation definition: rd wr operation 1 0 boot rom/eeprom read 0 1 boot rom/eeprom write 1 1 eeprom re-load operation (sr=1) if rd=1 and wr=1, then a eeprom re-load operation is enabled, the entire content of boot rom will be reloaded just like the auto-load function after power-up or hardware reset. 12 br boot rom select, set to select boot rom only if csr9<11>=0. 11 sr serial rom select, set to select serial rom for either read or write operation. 7:0 data if boot rom is selected ( csr9<12> is set ), this field contains the data to be read from and written to the boot rom. if serial rom is selected, csr9<3:0> are defined as follows: 3 sdo serial rom data out from serial rom into mx98715/MX98725. 2 sdi serial rom data input to serial rom from mx98715/MX98725. 1 sclk serial clock output to serial rom. 0 scs chip select output to serial rom. warning : csr9<11> and csr9<12> should be mutually exclusive for correct operations. 5.2.11 general purpose timer ( csr11 ) 5.2.10 flash memory programming address register ( csr10 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit 17:0=boot rom address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 con-continuous mode timer value field name description 16 con when set,the general purpose timer is in continuous operating mode. when reset, the timer is in one-shot mode. 15:0 timer value contains the timer value in a cycle time of 204.8us.
23 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.2.12 10 base-t status port ( csr12 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lpc-link partner's link code word lpn-link partner negotiable ans-autonegotiation arbitration state trf-transmit remote fault aps-autopolarity state ls10-link status of 10 base-t ls100-link status of 100 base-tx *software reset has no effect on this register field name decription 31:16 lpc link par tners link code word, where bit 16 is s0 ( selector field bit 0 ) and bit 31 is np ( next page ). effective only when csr12<15> is read as a logical 1. the following field. 15 lpn link partner negotiable, set when link partner support nway algorithm and csr14<7> is set. 14:12 ans autonegotiation arbitration state, arbitration states are defined 000 = autonegotiation disable 001 = transmit disable 010 = ability detect 011 = acknowledge detect 100 = complete acknowledge detect 101 = flp link good; autonegotiation complete 110 = link check when autonegotiation is completed, an anc interrupt ( csr5<4>) is generated, write 001 into this field can restart the autonegotiation sequence if csr14<7> is set. otherwise, these bits should be 0. 11 trf transmit remote fault 3 aps autopolarity state, set when polarity is positive. when reset, the 10base-t polarity is negative. the received bit stream is inverted by the receiver. 2 ls10 set when link status of 10 base-t port link test fail. reset when 10 base-t link test is in pass state. 1 ls100 link state of 100 base-tx, this bit reflects the state of sd pin, effective only when csr6<23>= 1 ( pcs is set ). set to indicate a fail condition .i.e. sd=0.
24 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.2.14 10 base-t control port (csr14) 5.2.13 sia reset register (csr13) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100 tx reset- 100 base-tx phy level reset nway reset- nway and 10 base-t phy level reset field name decription 0 nway reset while writing 0 to this bit, resets the csr12 & csr14. 1 100base-tx reset write a 1 will reset the internal 100 base-tx phy module . field name decription 18 t4 bit 9 of link code word for t4 mode. 17 txf bit 8 of link code word for 100 base-tx full duplex mode. 16 txh bit 7 of link code word for 100 base-tx half duplex mode. meaningful only when csr14<7> ( ane ) is set. 12 lte link test enable, when set the 10 base-t port link test function is enabled. 8 rsq receive squelch enable for 10 base-t port. set to enable. 7 ane autonegotiation enable, . 6 hde half-duplex enable, this is the bit 5 of link code word, only meaningful when csr14<7> is set. 2 pwd10b reset to power down 10 base-t module, this will force both tx and rx port into tri-state and prevent ac current path. set for normal 10 base t operation. 1 lbk loop back enable for 10 base-t mcc. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t4-100 base-t4 (link code word) txf-100 base-tx full duplex (link code word) txh-100 base-tx half duplex (link code word) lte-link test enable rso-receive squelch enable ane-autonegotiation enable hde-half duplex enable) pwd10b-power down 10 base-t lbk-loopback (mcc)
25 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.2.15 watchdog timer ( csr15) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mbz-must be zero rwr-receive watchdog release pwd-receive watchdog disable jck-jabber clock huj-host unjabber jab-jabber disable field name description 5 rwr defines the time interval no carrier from receive watchdog expiration until reenabling the receive channel. when set, the receive watchdog is release 40-48 bit times from the last carrier deassertion. when reset, the receive watchdog is released 16 to 24 bit times from the last carrier deassertion. 4 rwd when set, the receive watchdog counter is disable. when reset, receive carriers longer than 2560 bytes are guaranted to cause the watchdog counter to time out. packets horter than 2048 bytes are guaranted to pass. 2 jck when set, transmission is cut off after a range of 2048 bytes to 2560 bytes is transmitted, when reset, transmission for the 10 base-t port is cut off after a range of 26 ms to 33ms. when reset, transmission for the 100 base-tx port is cut off after a range of 2.6ms to 3.3ms.1 1 huj defines the time interval between transmit jabber expiration until reenabling of the transmit channel. when set, the transmit channel is released immediately after the jabber expiration. when reset, the jabber is released 365ms to 420 ms after jabber expiration for 10 base-t port. when reset, the jabber is released 36.5ms to 42ms after the jabber exporation for 100 base-tx port. 0 jbd jabber disable, set to disable transmit jabber function.
26 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.2.16 magic packet register ( csr16 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mpe (magic packet enable) field name description bit 31:23 reserved bit 22 mpe magic packet enable, set to enable magic packet mode bit 21:0 reserved sleep mode and mpe mode can be used seperately. when sleep and mpe are both set, the sleep mode dominate mpe, i.e., no magic packet can be detected since both tx and rx channel are shut off in sleep mode. on the detection of magic packet, a negative pulse will be asserted on pme# pin on pci bus, lanwake pin will be asserted high and exstart# pin is driven low and stay low even after pci reset is asserted. exstart# pin can be reset by device driver. 5.2.17 nway status register ( csr20 ) field name description 31 t4 t4 mode is accepted, read only 30 100txf 100base-tx full duplex is accepted, read only 29 100txh 100base-tx half duplex is accepted, read only 28 10txf 10base-t duplex is accepted, read only 27 10txh 10base-t half duplex is accepted, read only 16 reserved reserved for test purpose, must be set 1 for normal operation. 12 reserved reserved for test purpose, must be set 1 for normal operation. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100t4 100txf 100txh 10txf 10txh reserved reserved
27 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 5.3 power management functions : mx98715a complies to acpi version 1.0, supports d3cold state to generate pmeb. there are basically 3 power saving modes supported, namely remote power- on, remote wake-up, and sleep mode. by default, mx98715a will enable acpi function with the following registers setup : pfcs<20> ( new capability )= 1 pfcp<7:0> ( capability pointer ) = 44h ppmc<7:0> ( capability id ) = 1h please refer to pci configuration registers for more de- tails. 5.3.1 remote power-on mode : when ac power cord of pc is plugged into the wall outlet, mx98715a will load the network id from eeprom and enter itself into remote power-on mode automatically. the host and pci bus has no power at this stage. as soon as a magic packet addressed to this network adaptor, pmeb will be asserted low to power on the pc. to set up the remote power-on ( rpo ) mode, as long as a 5.0v standby vdd is connected into the adaptor's isolated vdd and mx98715a will set up itself to detect magic packet. no registers needed to be programmed. simply turn off the power switch or plug in the ac power cord of the pc that support rpo and everything else is set automatically. 5.3.2 remote wake-up mode : when the pc is still turned on regardless of the status of cpu and system's status, a magic packet can be detected if enabled. as soon as a magic packet ad- dressed to the network adaptor is detected, both inta# and pmeb can be asserted low if registers set up as follows : csr16<22> ( pme ) = 1 and ppmcsr<8> ( pme_en ) =1 to enable pmeb assertion. csr16<22> ( pme ) = 1 and csr7<28> ( mpie ) = 1 to enable inta# assertion 5.3.3 sleep mode : set pfda<31> ( sleep ) = 1 will enter the chip into a sleep mode where no tx nor rx activities can be pro- cessed. only pci configuration can be accessed.
28 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 6. ac/dc characteristics 6.1 boot rom timing (read) trc bpa 15-0 toes tce bceb boeb (ce&oe is typical shorted) toh bpd 7:0 tac c toolz tcolz toh 6.2 ac characteristics symbol description minimum typical maximum units trc read cycle 8 - - pci cycle tce chip enable access time - - 7 pci cycle tacc address access time - - 7 pci cycle toes output enable access time - - 7 pci cycl toh output hold from address, ceb, or oeb 0 - - ns pci cycle range:66ns (16mhz)~25ns (40mhz)
29 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 6.3 command write timing waveforms tas fcsb twp tah foeb fweb valid tdh bpd 7:0 bpa17-0 tds highz din symbol description minimum typical maximum units twp write pulse width 8 - pci cycle tas address setup time 0 - ns tah address hold time 7 - pci cycle tds data setup time 7 - pci cycl tdh data hold time 1 - pci cycle pci cycle range:66ns (16mhz)~25ns (40mhz) 6.4 absolute operation condition supply voltage (vcc) -0.5v to +7.0v dc input voltage (vin) 4.75v to 5.25v dc output voltage (vout) -0.5v to vcc +0.5v storage temperature range (tstg) -55 c to +150 c operating temperature range 0 c to 70 c power dissipation (pd) 750mw (typ) lead temp. (tl) (soldering, 10 sec) 260 c esd rating (rzap=1.5k, czap=100pf) 1.0kv clamp diode current 20ma
30 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 6.5 dc characteristics symbol parameter conditions min max units ttl/pci input/output voh minimum high level output voltage ioh = -3ma 2.4 v vol maximum low level output voltage iol = +6ma 0.4 v vih minimum high level input voltage 2.0 v vil maximum low level input voltage 0.8 v iin input current vi = vcc or gnd - 1.0 + 1.0 ua ioz minimum tri-state output leakage current vout = vcc or gnd -10 +10 ua led output driver vlol led turn on output voltage iol = 16ma 0.4 v supply idd average supply current ckref =25mhz 130 170 ma pciclk = 33mhz vdd average supply voltage 4.75v 5.25v v
31 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 revision history revision destription page date 1.7 (1) revise pfrv register bit 31-24 to be 2h 7 sep/15/1998 (2) exchange description for pfit register bit 7-0 and bit 15-8 9 (3) revise led2sel default setting to be link speed (10/100) 21 (4) revise esd rating in section 6.4 from 1.5kv to 1.0kv 29 (5) add power dissipation in section 6.4 to be 750mw (typ) 29 (6) add idd value in section 6.5 to be 130 ma to 170ma 30
32 p/n:pm0488 rev. 1.7, sep. 15, 1998 MX98725 7.0 package information 160-pin plastic quad flat pack item millimeters inches a 31.20 . 30 1.228 . 12 b 28.00 . 10 1.102 .004 c 28.00 . 10 1.102 . 004 d 31.20 . 30 1.228 . 012 e 25.35 .999 f 1.33 [ref.] .052 [ref.] g 1.33 [ref.] .052 [ref.] h .30 [typ.] .012 [typ.] i .65 [typ.] .026 [typ.] j 1.60 [ref.] .063 [ref.] k .80 . 20 .031 . 008 l .15 [typ.] .006 [typ.] m .10 max. .004 max. n 3.35 max. .132 max. o .10 min. .004 min. p 3.68 max. .145 max. note: each lead centerline is located within .25 mm[.01 inch] of its true position [tp] at maximum material condition. f n m k l j p o ecd 40 1 80 81 120 121 160 41 i h g b a
m acronix i nternational c o., l td. headquarters: tel:+886-3-578-8888 fax:+886-3-578-8887 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-747-2309 fax:+65-748-4090 taipei office: tel:+886-3-509-3300 fax:+886-3-509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the rignt to change product and specifications without notice. 33 MX98725

▲Up To Search▲

Price & Availability of MX98725

	To Download MX98725 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .